AN735 vishay siliconix document number: 71344 16-nov-00 www.vishay.com 1 designing a low-noise low-dropout regulator with the si9183 nitin kalje vishay?s si9183dt is a high-performance cmos ldo that offers one of the lowest dropout voltages in the industry in a space-saving 150-ma sot23-5 package. low dropout regulators (ldo) provide a regulated output power in battery-operated portable systems. the low dropout characteristic extends the lower operating voltage limit of the power source, thus prolonging the battery life. in addition, the low insertion loss and high ripple rejection ratio of ldos help to reduce system noise. cell phones, pdas, and other battery-powered portable devices, require a well designed power management architecture. selecting the right components for power-management circuitry prolongs battery life by ef ficiently processing the power and routing any reserved power to higher functions and/or standby time. the si9183dt?s ldo characteristics are superior as determined by its low dropout voltage, ground current, peak output current capability, power dissipation noise and ripple rejection specifications. the regulator is suitable for portable and noise-sensitive appliances such as cellular phones, and, due to its low dropout voltage, is ideal as a post-regulator for switch mode power converters. figure 1. 150-ma cmos ldo regulator (fixed output) c in 1.0 f v in 1 sd 3 on off 2 gnd rfb2 rfb1 ? + 1.215 v v ref ? 4bp + 5 c out 2.2 f v out 6 m switches shown for device in normal operating mode (sd = high)
AN735 vishay siliconix www.vishay.com 2 document number: 71344 16-nov-00
choosing the right series pass element for the regulator is key to achieving low dropout voltages and high efficiency. ldo regulators are functionally no dif ferent than variable resistance series elements, where the voltage drop across the pass element is equal to the input-to-output voltage differential. the variable resistor can either be a bipolar transistor, controlled by the base current, or a cmos transistor, which is controlled by the gate voltage. the series pass element operates in two different regions depending upon the input voltage. if the input voltage is higher than the output voltage, the p-channel power mosfet operates in the saturation region and acts as a controlled current source . this drain current is a function of the transconductance of the power mosfet g m di d dv . when the input voltage decreases to (v out + (r on i out )), the voltage regulator cannot maintain a regulated output. if the input voltage falls below this voltage, the p-channel power mosfet enters a linear region. in this linear region, the gate voltage changes with input voltage, and is not a function of the output or control voltage. all the circuits in the si9183dt are designed to operate with input voltages as low as 2 v and output voltages down to 1.5 v. the maximum gate-to-source voltage (v gs ) is the same as the input voltage at any load or input-to-output differential. the gate-to-source voltage should be high enough to operate the p-channel mosfet in the saturation region. the available drain current is proportional to the square of the difference between the applied and threshold gate voltage. the si9183dt gate threshold is 0.8 v and needs a minimum v gs of 1.8 v to produce a 300-ma peak current, which can be drawn for 2 ms. the package is designed to handle the power dissipated during the peak current pulse period. a low junction-to-lead thermal resistance enhances the power-handling capability of the si9183dt. the basic objective of closed-loop compensation is to increase the stability of the feedback loop. this is achieved by keeping the total phase lag encountered to less than 360 for a signal having a total gain of greater than or equal to unity. the phase lag includes the 180 phase change caused by the negative feedback. high closed-loop bandwidth with a solid phase margin reduces the response time and improves the dynamic line and load characteristic. the closed loop has two poles for the si9183. a low frequency pole, p o , is a result of output capacitance c out and the channel length modulation parameter of the p-channel mosfet. the location of this pole changes with the output load. the second pole is introduced by the compensation capacitor, parasitics of the series pass element, and the error amplifier of the regulator. the error amplifier output impedance and the gate capacitance of the power mosfet determine the location of the second pole. the si9183dt uses an internal zero to achieve a stable feedback loop that eliminates the need to rely on the esr value of output capacitors for a zero. the location of the internal zero is changed to offset any effect of the load on the low frequency pole p o . this internal zero offers the freedom to use a low-esr ceramic x5r or y5v capacitor for lower output noise. by means of the internal compensation of the si9183dt, a closed-loop bandwidth as high as 100 khz can be achieved easily with a phase margin no lower than 60 . see figure 2. ? 180 ? 120 ? 60 0 60 120 180 10 100 1000 10000 100000 1000000 ? 40 ? 20 0 20 40 60 80 10 100 1000 10000 100000 1000000 figure 2. closed loop bandwidth frequency (hz) gain (db) phase phase (deg) gain i out = 150 ma c in = 1 f c out = 2.2 f ceramic the circuit stability and output voltage during line and load step changes dominate the selection criteria of input and output capacitors. an input bypass capacitor is required in applications involving long inductive traces between the source and ldo. for shorter traces and lower source impedance applications, a 1- f ceramic capacitor is recommended. a higher step load at the output demands higher capacitance and a lower esr value at the output. a 2.2- f to 10- f ceramic capacitor with a y5v dielectric is recommended and an x5r dielectric is recommended for better temperature characteristics. the si9183dt requires only a small output capacitor because of a high closed-loop bandwidth of 100 khz or more. the unity gain cross-over frequency is lower at the higher output capacitance, as the low frequency pole p o appears lower on the frequency scale.
AN735 vishay siliconix document number: 71344 16-nov-00 www.vishay.com 3 the peak deviation to load transient is given by: v i step t response c out i step esr (1) where: i step = output step load (a) esr = esr of output capacitor ( ? ) t response = response time of the regulator (s) t response depends on the unity gain bandwidth and the phase margin of the closed loop. with a 2.2- f ceramic capacitor at the output, the maximum deviation observed in the output voltage is 25 mv, with less than a 3- s recovery time (refer to figures 3 and 4). the recovery time of the output from overshoot during the load removal depends on the amount of overshoot, the output capacitor, and the load current. the si9183dt is provided with an on/off control pin (named sd ), which opens and closes the internal power mosfet switch and controls the total current drawn by the entire circuit. the current in shutdown mode is less than 1 a, reducing the drain on the battery in standby mode and increasing standby time. while a low at sd pin opens the switch, a high at the sd pin enables the regulator operation. this allows the si9183dt to be used as a high-current, simple-disconnect switch that produces a regulated output. it is recommended that the user connect the sd pin to the input v in when not in use. the output terminal is pulled low internally to quickly discharge the output capacitor when sd is pulled low. the internal pull down is approximately 150 and requires 2 ms to discharge the 2.2- f output capacitor. refer to figures 5 and 6 for turn-on and turn-off of waveforms. v out 10 mv/div i load 100 ma/div v out = 3.0 v c in = 1 f c out = 2.2 f i load = 1 to 150 ma t rise = 2 sec v in = 4.0 v figure 3. load transient response ? 1 v out 10 mv/div i load 100 ma/div v out = 3.0 v c in = 1 f c out = 2.2 f i load = 150 to 1 ma t fall = 2 sec v in = 4.0 v figure 4. load transient response ? 2 figure 5. si9183dt ? turn-on through sd m 100 s/div sd (5 v/div) v out (2 v/div) figure 6. si9183dt ? turn-off through sd m 2.00 ms/div v out (2 v/div) sd (5 v/div) m 5.00 s/div v in = 3.5 v v out = 2.5 v i out = 0 ma c in = 1 f c out = 2.2 f v in = 3.5 v v out = 2.5 v i out = 0 ma c in = 1 f c out = 2.2 f m 5.00 s/div
AN735 vishay siliconix www.vishay.com 4 document number: 71344 16-nov-00 the si9183dt is available in two versions. version a has a fixed output and the provision for bypassing the bandgap reference for lower noise. the fixed output options are 1.5 v, 1.8 v, 2.0 v, 2.5 v, 2.8 v, 3.0 v, 3.3 v, 3.6 v, and 5.0 v. in version b, the non-inverting input of the error amplifier is connected to the fb pin to provide an adjustable output. the lower resistor r2 of the sensing network should be in the 25-k to 150-k range for low power consumption while maintaining adequate noise immunity. (refer to figures 7 and 8). calculate the high-side resistor using the equation: r1 v out 1.215 1.215 r2 (2) figure 7. version a with low output noise figure 8. version b with adjustable output 3 2 si9183-a 1 4 5 v in gnd sd v out bp v in sd v out 1 f 2.2 f sot-23, 5-lead 3 2 si9183-b 1 4 5 v in gnd sd v out fb v in sd v out 1 f 2.2 f sot-23, 5-lead 0.1 f r1 r2 the si9183dt is rated to deliver up to a 300-ma peak current for 2 ms. this maximum load current is specified for continuous operation and for finite pulse widths. maximum allowable junction temperature, junction-to-ambient thermal impedance at a thermal equilibrium, and the ambient temperature all determine the continuous current rating at a given input-to-output differential. the input voltage, p-channel power mosfet transconductance, and the transient thermal impedance between the junction and lead are major issues for the peak current amplitude and the pulse width. the maximum power dissipation allows for a safe junction temperature and is calculated using the following equation: (3) p dmax 150 t a ja p d v in v out i out v in i gnd efficiency v out i out v in i out i gnd where: ja = 180 c/w (all leads soldered to pc board on 1-oz copper) short circuit in the event of a short circuit in the load powered by an ldo, the si9183dt limits the maximum current to prevent damage to the electronics. the peak current through the si9183dt is typically limited to 400 ma during a continuous short circuit at the output. refer to figure 9. the current overshoot at the short circuit is an output capacitor discharge. the si9183 uses low capacitor, limiting the total energy discharge in the electronics. m 2.00 s/div v in = v out + 1 c out = 2.2 f c in = 1 f figure 9. output short circuit current v out 2 v/div i out 500 ma/div
AN735 vishay siliconix document number: 71344 16-nov-00 www.vishay.com 5 over-temperature the si9183dt is designed with an over-temperature protection circuit to prevent thermal runaway in the p-channel power mosfet. if the temperature reaches 165 c, an internal control circuit shuts off the p-channel power mosfet. the ldo will be disabled until the chip temperature drops below 145 c, and will re-engage automatically. the 20 c temperature difference avoids possible oscillation and reduces the average power delivery during fault conditions to reduce the risk of damage. refer to figure 10. m 1.00 s/div figure 10. output short circuit protection v out 2 v/div i out 500 ma/div v in = v out + 1 c out = 2.2 f c in = 1 f pcb layout the component placement around the ldo should be done carefully to achieve good dynamic line and load response. the input and noise capacitor should be kept close to the ldo. the rise in junction temperature depends on how efficiently the heat is carried away from junction-to-ambient. the junction-to-lead thermal impedance is a characteristic of the package and is fixed. the thermal impedance between lead-to-ambient can be reduced by increasing the copper area on pcb. increase the input, output and ground trace area to reduce the junction-to-ambient thermal impedance.
|
